1. Field of the Invention
The present invention relates to a reordering apparatus that changes a processing order of a plurality of processing subjects, the processing subjects being instructions within an information processing device, packets within a packet transmitting and receiving device, and the like.
2. Description of the Related Art
In an instruction handling process performed by an information processing device, a reordering control that issues instructions in the sequence that ones ready to issue come ahead, rather than in the order that they have arrived, maybe performed. In this case, the instructions are realigned from in the arrival order to in which the instructions marked issuable precede, as shown in FIG. 1.
In this way, a plural number of instructions should be maintained simultaneously, but when it issues an instruction that is issuable while others arrived earlier are not, the average latency from the arrival to the issuance should be reduced, thereby to shorten the overall execution time.
The reordering controls like above, are conventionally implemented in microprocessors, magnetic disk devices, tape devices, and so on to optimize instruction processing (for example, refer to Patent Documents 1 to 3, below).
Patent Document 1: Japanese Laid-open Patent Application No. 08-110901
Patent Document 2: Japanese Laid-open Patent Application No. 2000-048549
Patent Document 3: Japanese Laid-open Patent Application No. 2002-304823
However, in a conventional reordering control, a complicated operation is required to retrieve instructions, searching which one can be issued while they keep aligned in the arrival order, and a certain amount of processing time is also required. However, a quick and accurate decision is desired concerning which instruction to issue when plural instructions are ready, to further shorten instruction execution time.